In computer systems, the PCI (peripheral component interconnect) architecture defines a method to do configuration of PCI devices connected within the system whereby each PHB (PCI Host Bridge) has a CONFIG.sub.-- DATA and a CONFIG.sub.-- ADDRESS register. The address of each particular PCI device is set into the CONFIG.sub.-- ADDRESS register of the PHB "above" the PCI device, and then "read" ("load") and "write" ("store") operations are done to the PHB CONFIG.sub.-- DATA register which acts as a data port to the corresponding PCI devices "below" the corresponding PHBs.
In addition, the method describes that all PHBs are to "watch" for a write request to a particular address, and when such write operations are detected, the PHBs "stuff" the data into the CONFIG.sub.-- ADDRESS register of the PHB but no response is made to the write request, except by one PHB in the system which is designated to respond. Pulling data off the bus as the data "flies by" and not actually responding to the sender is sometimes referred to in the art as "snarting". When the write or read operation is performed to the single address designated for the CONFIG.sub.-- DATA register, all PHBs "see" this operation and if the contents of the particular PHB's CONFIG.sub.-- ADDRESS register indicate that the particular operation is destined for a PCI device "beneath" that PHB, then that PHB responds to the operation.
That approach assumes that all PHBs are on a common system bus. However, this is not the case in large hierarchical systems. In such systems, "address decodes" are used at various places to direct an operation to its final destination. Such routing decodes need to be architecture-independent and therefore such systems cannot do a "broadcast" of a PCI CONFIG.sub.-- DATA or CONFIG.sub.-- ADDRESS register operation so that all PHBs in the system "see" the operation.
Thus there is a need for an enhanced PCI configuration system and methodology which is scalable for use in large hierarchical computer systems.